1. Field of the Invention
The present invention relates generally to a method of forming a semiconductor device, and more particularly, to a method of forming a semiconductor device including a gate structure disposed on a fin structure with a light spacer pull down.
2. Description of the Prior Art
With the increasing miniaturization of semiconductor devices, various Fin-shaped field effect transistor (FinFET) devices have been developed. The Fin-shaped field effect transistor (FinFET) is advantageous for the following reasons. First, manufacturing processes of Fin-shaped field effect transistor (FinFET) devices are similar to traditional logic device processes, and thus are more compatible. In addition, since the three-dimensional structure of the FinFET increases the overlapping area between the gate and the fin, the channel region is controlled more effectively. This reduces a drain-induced barrier lowering (DIBL) effect and short channel effect. Moreover, the channel region is bigger for the same gate width, which means that the current between the source and the drain is increased.
In a current FinFET process, a gate structure (which may include a gate dielectric layer, a gate conductive layer located on the gate dielectric layer, and a cap layer located on the gate conductive layer) is formed on a substrate having at least a fin-shaped structure. A dielectric material layer is formed and a blanket etching process is performed to partially remove the dielectric material layer, so that a spacer is formed beside the gate structure.
After the formation of the spacer, an unwanted dielectric material layer remains may exist at the sidewall of the fin-shaped structure. To prevent the formation of the dielectric material layer remains, an etchant/chemical solvent which has a high removal rate or a long etching process time can be used in the blanket etching process to form the spacer beside the gate structure. This may induce serious spacer pull down, however, which causes the gate conductive layer to be exposed. Accordingly, a semiconductor process—more specifically a FinFET process including a gate spacer process—that can simultaneously prevent remaining unwanted spacer material as well as reducing spacer pull down to thereby improve the performance and reliability of the semiconductor device is needed in the industry.